"Generating Multi-cycle and Multiple Transient Fault Resilient Design ..."

Anirban Sengupta, Deepak Kachave (2016)

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DOI: 10.1109/ISVLSI.2016.11

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Anirban Sengupta, Deepak Kachave:
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. ISVLSI 2016: 75-80

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