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"Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs."

Liancheng Jia et al. (2021)

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DOI: 10.1109/ISVLSI51109.2021.00050

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-30

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  dblp key:
  - conf/isvlsi/JiaLL021
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  - https://dblp.org/rec/conf/isvlsi/JiaLL021
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang:
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs. ISVLSI 2021: 230-235

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