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"Design of a Low Power, High Speed Complementary Input Folded Regulated ..."

Manas Kumar Hati, Tarun Kanti Bhattacharyya (2011)

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DOI: 10.1109/ISVLSI.2011.9

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/isvlsi/HatiB11
Manas Kumar Hati, Tarun Kanti Bhattacharyya:
Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC. ISVLSI 2011: 114-119

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