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"A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock ..."

Yutaka Yoshida et al. (2007)

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DOI: 10.1109/ISSCC.2007.373607

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/isscc/YoshidaKHSNHHTIUOTKK07
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/YoshidaKHSNHHTIUOTKK07
Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. ISSCC 2007: 100-590

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