"A 16-Core RISC Microprocessor with Network Extensions."

Vishnu Yalala et al. (2006)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2006.1696061

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/YalalaBCHJKKVX06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/YalalaBCHJKKVX06
Vishnu Yalala, Derek Brasili, David Carlson, Adam Hughes, Anil Jain, Tim Kiszely, Kolar Kodandapani, Anand Varadharajan, Thucydides Xanthopoulos:
A 16-Core RISC Microprocessor with Network Extensions. ISSCC 2006: 305-314

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.