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"A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation ..."

Harold Pilo et al. (2011)

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DOI: 10.1109/ISSCC.2011.5746307

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-29

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  - conf/isscc/PiloABBGHLPSCKR11
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Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens:
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. ISSCC 2011: 254-256

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