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"An 800MS/s dual-residue pipeline ADC in 40nm CMOS."

Jan Mulder et al. (2011)

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DOI: 10.1109/ISSCC.2011.5746274

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  dblp key:
  - conf/isscc/MulderGVWAWWB11
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  - https://dblp.org/rec/conf/isscc/MulderGVWAWWB11
Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC 2011: 184-186

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