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"A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface ..."

Noriyuki Miura et al. (2011)

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DOI: 10.1109/ISSCC.2011.5746410

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda:
A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. ISSCC 2011: 490-492

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