"36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in ..."

Mu-Shan Lin et al. (2025)

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DOI: 10.1109/ISSCC49661.2025.10904767

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type: Conference or Workshop Paper

metadata version: 2025-04-25

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Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan J. Drake, Chin-Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem:
36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. ISSCC 2025: 586-588

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