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"A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 ..."

Kibong Koo et al. (2012)

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DOI: 10.1109/ISSCC.2012.6176869

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-11

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  dblp key:
  - conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12
Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim:
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. ISSCC 2012: 40-41

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