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"18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter ..."

Hye-Yoon Joo et al. (2016)

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DOI: 10.1109/ISSCC.2016.7418033

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  - https://dblp.org/rec/conf/isscc/JooBSKHA0KKKCSK16
Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. ISSCC 2016: 314-315

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