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"An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs ..."

Masayuki Ito et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523071

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/isscc/ItoHYHHNYHTMUOSMKK08
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  - https://dblp.org/rec/conf/isscc/ItoHYHHNYHTMUOSMKK08
Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91

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