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"26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW ..."

Hyeok-Ki Hong et al. (2015)

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DOI: 10.1109/ISSCC.2015.7063130

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. ISSCC 2015: 1-3

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