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"13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power ..."

Koji Hirairi et al. (2012)

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DOI: 10.1109/ISSCC.2012.6177102

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488

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