"A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration ..."

Jin-Hyeok Baek et al. (2025)

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DOI: 10.1109/ISSCC49661.2025.10904794

access: closed

type: Conference or Workshop Paper

metadata version: 2025-04-25

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Jin-Hyeok Baek, Jang-Hoo Kim, Yoo-Chang Sung, Jae-Woo Jeong, Jin-Kwan Park, Hyun-Kyu Oh, Bo-Hyeon Lee, Dong-Wan Ko, Tae-Seob Oh, Seung-Gi Hong, Chang-Ki Kwon, Daihyun Lim, Myeong-O. Kim, Seung-Jun Bae, Tae-Young Oh, Sang-Jun Hwang:
A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5^th-Generation 10nm DRAM Process. ISSCC 2025: 510-512

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