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"A fully pipelined implementation of Monte Carlo based SSTA on FPGAs."

Hiroshi Yuasa et al. (2011)

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DOI: 10.1109/ISQED.2011.5770818

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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  dblp key:
  - conf/isqed/YuasaTOS11
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  - https://dblp.org/rec/conf/isqed/YuasaTOS11
Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED 2011: 785-790

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