"Low power data-aware STT-RAM based hybrid cache architecture."

Mohsen Imani, Shruti Patil, Tajana Simunic Rosing (2016)

Details and statistics

DOI: 10.1109/ISQED.2016.7479181

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-12

a service of  Schloss Dagstuhl - Leibniz Center for Informatics