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"Digital PHY Design Methodologies for High-Speed and Low-Power Memory ..."

Kwanyeob Chae et al. (2018)

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DOI: 10.1109/ISOCC.2018.8649918

access: closed

type: Conference or Workshop Paper

metadata version: 2019-03-05

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  dblp key:
  - conf/isocc/ChaeKOPSP18
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Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park:
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. ISOCC 2018: 140-141

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