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"A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge ..."

Changseon Chae et al. (2021)

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DOI: 10.1109/ISOCC53507.2021.9613934

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-06

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  dblp key:
  - conf/isocc/ChaeKCP21
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  - https://dblp.org/rec/conf/isocc/ChaeKCP21
Changseon Chae, Subin Kim, Jonghang Choi, Jun-Eun Park:
A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices. ISOCC 2021: 421-422

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