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ORCID"Parallel Hardware Algorithms with Redundant Number Representations for ..."
Shoji Kawahito et al. (1992)
- Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura:
Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. ISMVL 1992: 337-345
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