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"A two-port SRAM for real-time video processor saving 53% of bitline power ..."

Hidehiro Fujiwara et al. (2006)

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DOI: 10.1145/1165573.1165589

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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  - conf/islped/FujiwaraNMMMKY06
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Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66

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