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"A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM ..."
Yi-Wei Chiu et al. (2013)
- Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang:
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED 2013: 51-56
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