Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Variable-latency adder (VL-adder): new arithmetic circuit design practice ..."

Yiran Chen et al. (2007)

> Home

Details and statistics

DOI: 10.1145/1283780.1283822

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/islped/ChenLLK07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/islped/ChenLLK07
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh:
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.