"A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep ..."

Swati et al. (2023)

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DOI: 10.1109/ISES58672.2023.00091

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-02

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Swati, Ranajoy Sadhukhan, Mitul Sudhirkumar Nagar, Pinalkumar Engineer:
A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices. iSES 2023: 409-412

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