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"Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT ..."

Harsha Keerthan Samudrala et al. (2018)

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DOI: 10.1109/ISES.2018.00015

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-22

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Harsha Keerthan Samudrala, Shaik A. Qadeer, Syed Azeemuddin, Mohammed Zafar Ali Khan:
Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm. iSES 2018: 21-26

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