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"Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap ..."

B. Naresh Kumar Reddy et al. (2023)

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DOI: 10.1109/ISES58672.2023.00090

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-02

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  dblp key:
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B. Naresh Kumar Reddy, K. Sarangam, Sushmita Dandeliya, S. Pavan Sai Naidu, Naveen Kumar P:
Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining. iSES 2023: 405-408

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