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"Logic Locking Designs at Transistor Level for Full Adders."

Sandeep Kolla et al. (2022)

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DOI: 10.1109/ISES54909.2022.00065

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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  dblp key:
  - conf/ises/KollaSVM22
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  - https://dblp.org/rec/conf/ises/KollaSVM22
Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Logic Locking Designs at Transistor Level for Full Adders. iSES 2022: 289-292

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