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"Design and Optimization of Single Electron Transistor Based 4-Bit ..."

Rathin K. Joshi, Rutu Parekh, Yash Agrawal (2017)

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DOI: 10.1109/INIS.2017.17

access: closed

type: Conference or Workshop Paper

metadata version: 2023-12-26

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Rathin K. Joshi, Rutu Parekh, Yash Agrawal:
Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation. iNIS 2017: 34-39

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