"An FPGA Based Hardware Accelerator for Classification of Handwritten Digits."

R. Gautham Sundar Ram et al. (2018)

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DOI: 10.1007/978-3-030-16657-1_88

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-20

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  - conf/isda/RamCSS18
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R. Gautham Sundar Ram, Nitin Chaturvedi, Sumeet Saurav, Sanjay Singh:
An FPGA Based Hardware Accelerator for Classification of Handwritten Digits. ISDA (1) 2018: 945-954

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