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"CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs."

Hamid R. Zarandi et al. (2007)

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DOI: 10.1109/ISCAS.2007.378640

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/iscas/ZarandiMPM07a
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  - https://dblp.org/rec/conf/iscas/ZarandiMPM07a
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew:
CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678

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