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"Multilevel timing-constrained full-chip routing in hierarchical quad-grid ..."
Jin-Tai Yan et al. (2006)
- Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang:
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS 2006
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