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"A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate ..."

Jun-Hong Weng et al. (2006)

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DOI: 10.1109/ISCAS.2006.1693274

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/iscas/WengTLY06
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Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang:
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. ISCAS 2006

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