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"Techniques to improve linearity of CMOS sample-and-hold circuits for ..."

Preetam Tadeparthy, M. Das (2002)

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DOI: 10.1109/ISCAS.2002.1010770

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Preetam Tadeparthy, M. Das:
Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps. ISCAS (5) 2002: 581-584

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