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"A parallel LSI architecture for LDPC decoder improving message-passing ..."

Kazunori Shimizu et al. (2006)

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DOI: 10.1109/ISCAS.2006.1693779

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006

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