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"A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit ..."

Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi (2006)

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DOI: 10.1109/ISCAS.2006.1693034

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
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Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi:
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. ISCAS 2006

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