"A leakage estimation and reduction technique for scaled CMOS logic ..."

Hafijur Rahman, Chaitali Chakrabarti (2004)

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type: Conference or Workshop Paper

metadata version: 2016-05-20

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Hafijur Rahman, Chaitali Chakrabarti:
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. ISCAS (2) 2004: 297-300

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