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"Inertial and degradation delay model for CMOS logic gates."
Jorge Juan-Chico et al. (2000)
- Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462
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