"Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar ..."

Masaki Ishida et al. (1994)

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DOI: 10.1109/ISCAS.1994.408826

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai:
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. ISCAS 1994: 411-414

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