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"Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved ..."

Jean Pierre T. Habimana, Francis Sabado, Jia Di (2016)

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DOI: 10.1109/ISCAS.2016.7527349

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Jean Pierre T. Habimana, Francis Sabado, Jia Di:
Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation. ISCAS 2016: 750-753

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