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"A low time-complexity, hardware-efficient bit-parallel power-sum circuit ..."

Jyh-Huei Guo, Chin-Liang Wang (1999)

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DOI: 10.1109/ISCAS.1999.777943

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Jyh-Huei Guo, Chin-Liang Wang:
A low time-complexity, hardware-efficient bit-parallel power-sum circuit for finite fields GF(2M). ISCAS (1) 1999: 521-524

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