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"A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA."

Zhiqiang Cui, Zhongfeng Wang (2006)

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DOI: 10.1109/ISCAS.2006.1693778

access: closed

type: Conference or Workshop Paper

metadata version: 2023-04-24

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Zhiqiang Cui, Zhongfeng Wang:
A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006

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