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"Gate-level dual-threshold static power optimization methodology (GDSPOM) ..."

B. Chung, J. B. Kuo (2006)

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DOI: 10.1109/ISCAS.2006.1693418

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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B. Chung, J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. ISCAS 2006

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