"PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer."

Qize Yang et al. (2025)

> Home

Details and statistics

DOI: 10.1145/3695053.3731045

access: closed

type: Conference or Workshop Paper

metadata version: 2025-07-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isca/YangWGLSDWLWZYH25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isca/YangWGLSDWLWZYH25
Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu:
PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. ISCA 2025: 49-64

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.