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"A Scalable VLSI Architecture for Binary Prefix Sums."
Rong Lin et al. (1998)
- Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya:
A Scalable VLSI Architecture for Binary Prefix Sums. IPPS/SPDP 1998: 333-337
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