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"Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling ..."

Hang-Ting Lue et al. (2024)

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DOI: 10.1109/IMW59701.2024.10536947

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-10

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Hang-Ting Lue, Wei-Chen Chen, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F² DRAM Below Equivalent 10nm Node. IMW 2024: 1-4

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