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"Low Latency FPGA Implementation of Izhikevich-Neuron Model."

Vitor V. Bandeira et al. (2015)

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DOI: 10.1007/978-3-319-90023-0_17

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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  dblp key:
  - conf/iess/BandeiraCBR15
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  - https://dblp.org/rec/conf/iess/BandeiraCBR15
Vitor V. Bandeira, Vivianne L. Costa, Guilherme Bontorin, Ricardo A. L. Reis:
Low Latency FPGA Implementation of Izhikevich-Neuron Model. IESS 2015: 210-217

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