"Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a ..."

Yashrajsinh Parmar, K. Sridharan (2018)

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DOI: 10.1109/IECON.2018.8591409

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-07

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Yashrajsinh Parmar, K. Sridharan:
Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation. IECON 2018: 3770-3775

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