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"Leverage Redundancy in Hardware Transactional Memory to Improve Cache ..."

Zhichao Yan et al. (2018)

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DOI: 10.1145/3225058.3225093

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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  dblp key:
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Zhichao Yan, Hong Jiang, Witawas Srisa-an, Sharad C. Seth, Yujuan Tan:
Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability. ICPP 2018: 60:1-60:10

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