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"QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA ..."

Chenyang Tu et al. (2015)

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DOI: 10.1007/978-3-319-29814-6_15

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  dblp key:
  - conf/icics/TuZGLML15
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Chenyang Tu, Jian Zhou, Neng Gao, Zeyi Liu, Yuan Ma, Zongbin Liu:
QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations. ICICS 2015: 184-198

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