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"An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires."

Ya-Chi Huang et al. (2018)

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DOI: 10.1109/ICICDT.2018.8399770

access: closed

type: Conference or Workshop Paper

metadata version: 2018-07-06

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  dblp key:
  - conf/icicdt/HuangCWG18
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  - https://dblp.org/rec/conf/icicdt/HuangCWG18
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Sumeet Kumar Gupta:
An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. ICICDT 2018: 117-120

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